|
Highlights of the TMS320C64x™ DSP Architecture and Core |
| The C64x™ DSP generation features TI's VelociTI.2™ VLIW architecture extensions that include support for packed data processing and special purpose instructions to accelerate broadband infrastructure and imaging applications. The C64x generation is shipping DSPs with clock speeds available up to 1 GHz and can incorporate multiple memory, peripheral and voltage combinations to address a wide range of high performance applications. |
C64x™ DSP architechture highlights include: |
| |
◎ VelociTI.2 architecture extensions with new instructions to accelerate performance in
....key applications
◎ Increased parallelism with quad 16-bit and octal 8-bit multiply-accumulate performance
◎ Improved orthogonality with frequently used instructions available in more functional units
◎ Double the bandwidth resulting from more registers, wider load/store data paths and
....enlarged 2-level cache
◎ Completely software compatible with TMS320C62x™ DSPs |
|
|
The C64x+™ DSP core architecture also includes: |
| |
◎ 32-bit multiply instructions for extended precision computation
◎ Expanded arithmetic functions to support FFT and DCT algorithms
◎ Improved complex multiplication support
◎ Double dot product instructions for improving throughput of FIR loops
◎ New Parallel packing Instructions
◎ Enhanced Galois Field Multiply |
|
|
|
| DaVinci™ Technology Peripheral Features |
| DaVinci Technology devices including TMS320C64x, TMS320DM644x and the new TMS320DM643x DSPs peripheral system includes a variety of features designed to help developers maximize the many performance advantages of the C64x™ DSP core: |
| |
◎ Enhanced Direct Memory Access (EDMA) Controller
◎ Peripheral Component Interconnect (PCI)
◎ Universal Test and Operation PHY Interface for ATM (UTOPIA)
◎ Viterbi Coprocessor (VCP)
◎ Turbo Coprocessor (TCP)
◎ External Memory Interfaces (EMIFs)
◎ Multi-channel Buffered Serial Ports (McBSPs)
◎ Host Port Interfaces (HPI)
◎ Direct Memory Access (DMA) Controller
◎ 32-bit Expansion Bus ("X-Bus") |
|
|
| Enhanced Direct Memory Access (EDMA) Controller |
| |
◎ 64 independent channels support various system dataflows
◎ Facilitates sophisticated transfers in background of CPU - Auto initializing, linking,
....chaining of channels
◎ 2.4 GB/s sustained bandwidth
◎ Unsurpassed efficiency and concurrency with the ability to automatically interleave traffic
....from multiple peripherals every cycle |
|
|
| Peripheral Component Interconnect (PCI) |
C6415 and C6416 DSPs: |
| |
◎ 32-bit/33 MHz, 3.3V Master/Slave Interface Conforms to PCI Specification 2.1
◎ Meets Requirements of PC99
◎ Access to Entire Memory Map
◎ Three PCI Bus Address Registers
......: Prefetchable Memory
......: Non-Prefetchable Memory I/O
◎ Four-Wire Serial EEPROM Interface
◎ PCI Interrupt Request Under DSP Program Control
◎ DSP Interrupt Via PCI I/O Cycle |
|
|
| DM642 DSP: |
|
| Universal Test and Operation PHY Interface for ATM (UTOPIA) |
| |
◎ Utopia Level 2 ATM controller- C6415/C6416
◎ 8-bit Transmit and Receive Operations up to 50 MHz
◎ User-defined cell format up to 64 bytes |
|
|
| Viterbi Coprocessor (VCP) - Applies to C6416 DSP only |
| |
◎ Supports > 500 voice channels at 8 Kbps
◎ Programmable decoder parameters include constraint length, code rate, and frame length |
|
|
| Turbo Coprocessor (TCP) - Applies to C6416 DSP only |
| |
◎ Supports 35 data channels at 384 kbps
◎ 3GPP/IS2000 Turbo coder
◎ Minimal processor delay
◎ Programmable parameters include mode, rate and frame length |
|
|
| External Memory Interfaces (EMIFs) |
| Other densely integrated on-chip peripherals common to various C6000™ DSPs include: |
| |
◎ Supports a glueless interface to several external devices including:
......- Synchronous burst SRAM (SBSRAM)
......- Synchronous DRAM (SDRAM)
......- Asynchronous devices including SRAM, ROM and FIFOs
......- An external shared-memory device
◎ C6414/C6415/C6416 DSPs Provide Dual 133 MHz EMIFs
......- 64-bit Interface for intended as a dedicated high speed interface to high
.........performance.industry.standard memories
......- 16-bit Interface for intended as a dedicated high speed interface to high
.........performance industry.standard memories
......- C6712 DSP has a single 16-bit EMIF
......- All other devices have a single 32-bit EMIF |
|
|
| Multi-channel Buffered Serial Ports (McBSPs) |
| |
◎ High-speed full-duplex serial ports
......- Full-Duplex communication
......- Double-buffered data registers for continuous data stream
◎ Direct interface to
......- C6000 devices
......- Industry-standard codecs, analog interface chips (AICs), and other serially
........connected A/D and D/A devices
◎ ST-BUS compliant devices supporting
......- T1/E1 framers
......- H.110/H.100 Framers
......- MVIP and SCSA interface device
......- IOM-2 compliant devices
......- AC97 compliant devices
......- IIS compliant devices
......- SPI™ devices
◎ Transmits and receives up to 128 channels
......- Select from 8-, 12-, 16-, 20-, 24-, or 32-bit data size
......- The C64x McBSPs support independent selection of up to 128 transmit and
....... 128 receive channels
......- The C62x/C67x McBSPs support independent selection of up to 32 transmit and
....... 32 receive channels
◎ Highly programmable internal clock & frame generation
◎ On-chip companding (COMpress & exPAND) hardware for data compression
.... /expansion in either μ-law or A-law format |
|
|
| Host Port Interfaces (HPI) |
| |
◎ 32/16-bit HPI on C6414/C6415/C6416/DM642
◎ 16-bit HPI on C6201/C6701/C6211/C6711/DM641
◎ Parallel port for host processor to directly access DSP's memory space
◎ The host device has ease of access because it is the master of the interface
◎ Host & DSP can exchange information via internal/external memory
◎ The host has direct access to memory-mapped peripherals |
|
|
| Direct Memory Access (DMA) Controller |
| Applies to C6201, C6202, C6203, C6204, C6205, C6701 DSPs only |
| |
◎ Transfers data between points in the memory space without CPU intervention
◎ Allows data movements to/from internal memory, external memory and peripherals to occur
....in background of CPU operation
◎ Operates independent of CPU
◎ Four programmable channels and a fifth auxiliary channel
◎ Enhanced DMA (EDMA) has 16 programmable channels as well as a RAM space to
... hold.multiple configurations for future transfers (C6x1x devices only) |
|
|
| 32-bit Expansion Bus ("X-Bus") |
| |
◎ Replaces the HPI on C6202, C6203 and C6204
◎ Expansion Bus host port can operate in either asynchronous slave mode (similar to HPI)
....or in synchronous master/slave mode
◎ Synchronous FIFOs and asynchronous peripheral I/O devices may interface to the
....Expansion Bus |
|
|
| |
